IC62C1024L

www.DataSheet4U.com IC62C1024L IC62C1024L .EATURES 128K x 8 LOW POWER CMOS STATIC RAM • High-speed access time: 35, 45, 55, 70 ns • Low active power: 450 mW (typical) • Low standby power: 150 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • .ully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (±10%) power supply performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. DESCRIPTION The 1+51 IC62C1024L is a low power,131,072-word by 8-bit CMOS static RAM. It is fabricated using 1+51 's high- When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62C1024L is available in 32-pin 600mil DIP, 450mil SOP and 8*20mm TSOP-1 packages. .UNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 x 2048 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publ...