ICS674-01

USER CONFIGURABLE DIVIDER DATASHEET ICS674-01 Description The ICS674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A and B Dividers can be cascaded to give a maximum divide of 669510. The ICS674-01 supports the ICS673 PLL Building Block and enables the user to build a full custom PLL synthesizer. Block Diagram Features Packaged in 28-pin SSOP (150 mil body) Pb (lead) free package, RoHS compliant General purpose programmable divider Supports ICS673 PLL Building Block User determines the divide by setting input pins Pull-ups on all select inputs Includes one 7-bit Divider for OUTA Includes one 9-bit Divider and one selectable Post Divider for OUTB Industrial temperature range available 25 mA drive capability at TTL levels Advanced, low power CMOS process Operating voltage of 3.3 V or 5 V A6:A0 7 VDD 2 Divider A INA (7-Bit) OUTA Divider B INB (9-Bit) Post Divider 9 B8:B0 3 GND 3 S2:S0 OUTB IDT™ / ICS™ USER CONFIGURABLE DIVIDER 1 ICS674-01 REV H 051310 ICS674-01 USER CONFIGURABLE DIVIDER CLOCK DIVIDER Pin Assignment A5 A6 S0 S1 S2 VDD INA INB GND B0 B1 B2 B3 B4 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 28 pin (150 mil)...