Low Skew, 1-to-4 Multiplexed Differential/ ICS8305I-02 LVCMOS-to-LVCMOS Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - ...
Low Skew, 1-to-4 Multiplexed Differential/ ICS8305I-02 LV
CMOS-to-LV
CMOS Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2016
DATA SHEET
General Description
The ICS8305I-02 is a low skew, 1-to-4, Differential/ LV
CMOS-to-LV
CMOS/LVTTL Fanout Buffer. The ICS8305I-02 has selectable clock inputs that accept either differential or single-ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the ICS8305I-02 ideal for those applications demanding well defined performance and repeatability.
Features
Four LV
CMOS/LVTTL outputs, (two banks of two LV
CMOS
outputs)
Selectable differential CLK, nCLK pair or LV
CMOS_CLK input CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL
LV
CMOS_CLK supports the following input types: LV
CMOS,
LVTTL
Maximum output frequency: 250MHz Output skew: 100ps (maximum)
Power supply modes:
Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V
-40°C to 85°C ambient operating temperature Lead-free (RoHS 6) packaging
For functional replacement device use 8305
Block Diagram
OEA Pullup CLK_EN Pullup
LV
CMOS_CLK Pulldown
00
CLK nCLK
Pulldown Pullup
11
...