DatasheetsPDF.com

ICS8305I Datasheet

Part Number ICS8305I
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Datasheet ICS8305I DatasheetICS8305I Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER FEATURES • 4 LVCMOS/LVTTL outputs • Selectable differential or LVCMOS/LVTTL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • Maximum output frequency: 350MHz • Output skew: 40ps (maximum) • Part-to-part skew: 700ps (maximum) • Additive phase jit.

  ICS8305I   ICS8305I






Part Number ICS8305I
Manufacturers Renesas
Logo Renesas
Description LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Datasheet ICS8305I DatasheetICS8305I Datasheet (PDF)

ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled.

  ICS8305I   ICS8305I







Part Number ICS8305I
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Datasheet ICS8305I DatasheetICS8305I Datasheet (PDF)

ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled.

  ICS8305I   ICS8305I







MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Circuit Systems, Inc. ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER FEATURES • 4 LVCMOS/LVTTL outputs • Selectable differential or LVCMOS/LVTTL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • Maximum output frequency: 350MHz • Output skew: 40ps (maximum) • Part-to-part skew: 700ps (maximum) • Additive phase jitter, RMS: 0.04ps (typical) • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply • -40°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant GENERAL DESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A sepawww.DataSheet4U.com rate output enable pin controls whether the outputs are in the active or high impedance state. ICS Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_EN D Q LE LVCMO.


2008-12-18 : ICS83021I    ICS83023I    ICS8302-01    ICS83023I    ICS83026I    ICS83026I-01    ICS83026I-01    ICS8302I-01    ICS83032I    ICS8304-01   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)