ICS8516I

Integrated Circuit Systems, Inc. ICS8516I LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP FEATURES 16 Differential LVDS outputs CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Maximum output frequency: 700MHz Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks Translates any single-ended input signal to LVDS with resistor bias on nCLK input Multiple output enable inputs for disabling unused outputs in reduced fanout applications LVDS compatible Output skew: 65ps (maximum) Part-to-part skew: 550ps (maximum) Propagation delay: 2.4ns (maximum) 3.3V operating supply -40°C to 85°C ambient operating temperature GENERAL DESCRIPTION The ICS8516I is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClock S ™ family of High Performance Clock Solutions from ICS. The ICS8516I CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516I provides a low power, low noise, point-to-point solution for distributing clock signals over controlled impedances of 100Ω . ICS Dual output enable inputs allow the ICS8516I to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the ICS8516I ideal for those application...