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ICS8602 Datasheet

Part Number ICS8602
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Datasheet ICS8602 DatasheetICS8602 Datasheet (PDF)

PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR FEATURES • Fully integrated PLL • 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequ.

  ICS8602   ICS8602






DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR FEATURES • Fully integrated PLL • 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 36ps (typical) • Output skew: 125ps (maximum) • Static Phase Offset: TBD±100ps (typical) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature GENERAL DESCRIPTION The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS/LVTTL Zero DeHiPerClockS™ lay Buffer and a member of the HiPerClockS™ family of High Performance Clocks Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The device is designed only for 1:1 input/output frequency ratios. The output divider allows a wide input/output frequency range with the 250MHz to www.DataSheet4U.com 500MHz VCO. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal out.


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