ICS95V842

ICS95V842 DDR Phase Lock Loop Clock Driver (60MHz - 220MHz) Recommended Application: 1:2 DDRI Clock Driver Product Description/Features: Low skew, low jitter PLL clock driver Feedback pins for input to output synchronization Spread Spectrum tolerant inputs With bypass mode mux Operating frequency 60 to 220 MHz Switching Characteristics: CYCLE - CYCLE jitter: <75ps OUTPUT - OUTPUT skew: <60ps Period jitter: ±75ps Half-Period jitter: ±75ps Pin Configuration VDD2.5 1 DDRT0 2 DDRC0 3 GND 4 CLK_INT 5 CLK_INC 6 AVDD 7 AGND 8 ICS95V842 16 GND 15 DDRC1 14 DDRT1 13 VDD2.5 12 FB_INC 11 FB_INT 10 FB_OUTT 9 FB_OUTC 16 pin SSOP Functionality INPUTS OUTPUTS PLL State AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC GND L H LH L H Bypassed/Off GND H L HL H L Bypassed/Off 2.5V (nom) L H LH L H On 2.5V (nom) H L HL H L On Block Diagram FB_INT FB_INC CLK_INC CLK_INT PLL FB_OUTT FB_OUTC DDRT (1:0) DDRC(1:0) AVDD 0830B—11/24/08 1 ICS95V842 Pin Descriptions PIN # 1 2 3 4 5 6 7 8 PIN NAME VDD2.5 DDRT0 DDRC0 GND CLK_INT CLK_INC AVDD AGND PIN TYPE PWR OUT OUT PWR IN IN PWR PWR 9 FB_OUTC OUT 10 FB_OUTT OUT 11 FB_INT IN 12 FB_INC 13 VDD2.5 14 DDRT1 15 DDRC1 16 GND IN PWR OUT OUT PWR DESCRIPTION Power supply, nominal 2.5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. "True" reference clock input. "Complementary" reference clock input. 3.3V Analog Power pin for Core PLL Analog Grou...