1.8V Wide Range Frequency Clock Driver
ICS97U8 7 7
1.8V Wide Range Frequency Clock Driver
Recommended Application: • DDR2 Memory Modules / Zero Delay Board F...
Description
ICS97U8 7 7
1.8V Wide Range Frequency Clock Driver
Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR DIMM logic solution with
ICSSSTU32864
Product Description/Features: Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution (SSTL_18) Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Auto PD when input signal is at a certain logic state
Switching Characteristics: Period jitter: 40ps Half-period jitter: 60ps CYCLE - CYCLE jitter 40ps OUTPUT - OUTPUT skew: 40ps
Pin Configuration
123456
A B C D E F G H J K
1
A CLKT1 B CLKC1 C CLKC2 D CLKT2 E CLK_INT F CLK_INC G AGND H AVDD J CLKT3 K CLKC3
52-Ball BGA
Top View
2
CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4
3
CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4
4
CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9
5
CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9
6
CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8
Block Diagram
OE OS AVDD
Powerdown Control and Test Logic
LD* or OE LD*, OS or OE
LD*
PLL bypass
CLK_INT CLK_INC
10K-100k PLL
GND
FB_INT FB_INC
* The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC.
CLKT0 CLKC0
CLKT1 CLKC1
CLKT2 CLKC2
CLKT3 CLKC3 CLKT4 CLKC4
CLKT5 CLKC5
CLKT6 CLKC6
CLKT7 CLKC7
CLKT8 CLKC8
CLKT9 CLKC9
FB_OUTT FB_OUTC
CLKC1 CLKT1 CLKT0 CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ
40
31
VDDQ 1 CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGN...
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