ICS98ULPA877A

Integrated Circuit Systems, Inc. ICS98ULPA877A www.DataSheet4U.com Advance Information 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR2 DIMM logic solution Product Description/Features: Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution (SSTL_18) Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Auto PD when input signal is at a certain logic state Switching Characteristics: Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667/800) Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667/800) OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) 30ps (DDR2-667/800) CYCLE - CYCLE jitter 40ps Pin Configuration 1 A B C D E F G H J K 2 3 4 5 6 52-Ball BGA Top View A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 CLKC1 CLKC0 CLKT1 Block Diagram OE OS AVDD LD or OE POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD (1) 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 CLKC5 CLKT0 VDDQ 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 CLKT5 CLKC6 CLKT6 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 VDDQ 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 CLKT0 39 32 35 34 37 40 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 38 36 33 31 CLKC0 VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND 1 2 3 4 5 ...