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DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
CONFIDENTIAL
ICSSSTUAF32868A
Descripti...
www.DataSheet4U.com
DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
CONFIDENTIAL
ICSSSTUAF32868A
Description
This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LV
CMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The ICSSSTUAF32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference
voltage (Vref) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LV
CMOS RESET and C inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to ...