IDT70T3509M

www.DataSheet4U.com HIGH-SPEED 2.5V 1024K x 36 IDT70T3509M SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 4.2ns (133MHz)(max.) – Industrial: 4.2ns (133MHz)(max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Interrupt Flags Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth) – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 133MHz – Fast 4.2ns clock to data out ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility Dual Cycle Deselect (DCD) for Pipelined Output Mode 2.5V (±100mV) power supply for core LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port Includes JTAG functionality Available in a 256-pin Ball Grid Array (BGA) Common BGA footprint provides design flexibility over seven density generations (512K to 36M-bit) Green parts available, see ordering information BE3R Functional Block Diagram BE3L BE2L BE1L BE0L BE2R BE1R BE0R FT/PIPEL 1/0 0a 1a a 0b 1b b 0c 1c c 0d 1d d 1d 0d d 1c 0c c 1b 0b b 1a 0a a 1/0 FT/PIPER R/ WL R/WR (2) (2) CE0L CE1L 1 0 1/0 B B B B B B B B W W WW W W W W ...