IDT70T631S

Features ◆ ◆ HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ ◆ ◆ ◆ PRELIMINARY IDT70T633/1S ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 8/10/12/15ns (max.) – Industrial: 10/12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T633/1 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ ◆ Full hardware support of semaphore signaling between ports on-chip On-chip port arbitration logic Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages Single 2.5V (±100mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 256-ball Ball Grid Array, 144-pin Thin Quad Flatpack and 208-ball fine pitch Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds UB R LB R Functional Block Diagram UBL LBL R/W L B E 0 L B E 1 L B E 1 R B E 0 R R/WR CE0L CE1L CE0R CE1R OEL Dout0-8_L D...