IDT70T9159L

www.DataSheet4U.com HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM .eatures x x PRELIMINARY IDT70T9169/59L x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial:7.5/9/12ns (max.) – Industrial: 9ns (max.) Low-power operation – IDT70T9169/59L Active: 225mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic x x x x Full synchronous operation on both ports – 4.0ns setup to clock and 0.5ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode LVTTL- compatible, single 2.5V (±100mV) power supply Industrial temperature range (–40°C to +85°C) is available for 66MHz Available in a 100-pin Thin Quad Flatpack (TQFP) and 100pin fine pitch Ball Grid Array (fpBGA) packages. .unctional Block Diagram R/WL OEL CE0L CE1L R/WR OER CE0R CE1R 1 0 0/1 1 0 0/1 FT/PIPEL 0/1 1 0 0 1 0/1 FT/PIPER I/O0L - I/O8L I/O0R - I/O8R I/O Control I/O Control A13L(1) A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A13R(1) A0R CLKR ADSR CNTENR CNTRSTR 5654 drw 01 NOTE: 1. A 13 is a NC for IDT70...