IDT70V261L

Š HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM ◆ IDT70V261S/L ◆ Features ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 25/35/55ns (max.) – Industrial: 25ns (max.) Low-power operation – IDT70V261S Active: 300mW (typ.) Standby: 3.3mW (typ.) – IDT70V261L Active: 300mW (typ.) Standby: 660µW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70V261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 3.3V (±0.3V) power supply Available in a 100-pin TQFP, Thin Quad Plastic Flatpack Industrial temperature range (-40°C to +85°C) is available for selected speed Green parts available, see ordering information Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL LBR CER OER I/O8L-I/O15L I/O0L-I/O7L BUSYL (1,2) I/O Control I/O Control I/O8R-I/O15R I/O0R-I/O7R BUSYR A13R A0R (1,2) A13L A0L Address Decoder 14 MEMORY ARRAY 14 Address Decoder CEL OEL R/WL SEML (2) INTL NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. ARBITRATION INTERRUPT SEMAPHORE LOGI...