DatasheetsPDF.com

IDT70V639S Datasheet

Part Number IDT70V639S
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
Datasheet IDT70V639S DatasheetIDT70V639S Datasheet (PDF)

HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM x PRELIMINARY IDT70V639S Features True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12/15ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V639 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S.

  IDT70V639S   IDT70V639S






HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM x PRELIMINARY IDT70V639S Features True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12/15ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V639 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports UBL LBL x x x x x x x x x x x x x x Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Supports JTAG features compliant to IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. LVTTL-compatible, single 3.3V (±150mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram UB R LB R R/W L B E 0 L B E 1 L B E 1 R B E 0 R R/WR CE0L CE 1L CE0R CE 1R OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R OER 128K x 18 MEMORY ARRAY I/O0L- I/.


2005-04-04 : TSC14    SN76002ND    MHW3628    EP2015CN    UC3844D    UC3844D    UC3844D    UC3844D    UC3844D1    SSP4N60B   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)