IDT71V2558SA

128K x 36, 256K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x www.DataSheet4U.com Single R/W (READ/WRITE) control pin x Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications x 4-word burst capability (interleaved or linear) x Individual byte write (BW1 - BW4) control (May tie active) x Three chip enables for simple depth expansion x 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ) x Optional - Boundary Scan JTAG Interface (IEEE 1149.1 complaint) x Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) x IDT71V2556S IDT71V2558S IDT71V2556SA IDT71V2558SA Features Description The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V2556/58 contain data I/O, address and contr...