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IDT71V432 Datasheet

Part Number IDT71V432
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect
Datasheet IDT71V432 DatasheetIDT71V432 Datasheet (PDF)

32K x 32 CacheRAM™ 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect Features x x IDT71V432 x x x x x x 32K x 32 memory configuration Supports high-performance system speed: Commercial and Industrial: — 5ns Clock-to-Data Access (100MHz) — 6ns Clock-to-Data Access (83MHz) — 7ns Clock-to-Data Access (66MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC32K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write c.

  IDT71V432   IDT71V432






Part Number IDT71V433
Manufacturers IDT
Logo IDT
Description Synchronous SRAM
Datasheet IDT71V432 DatasheetIDT71V433 Datasheet (PDF)

www.DataSheet4U.com 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs Features 32K x 32 memory configuration Supports high performance system speed: Commercial and Industrial: — 11 11ns Clock-to-Data Access (50MHz) — 12 12ns Clock-to-Data Access (50MHz) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Single 3.3V power supply (+10/-5%) Packaged in a JEDEC S.

  IDT71V432   IDT71V432







32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect

32K x 32 CacheRAM™ 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect Features x x IDT71V432 x x x x x x 32K x 32 memory configuration Supports high-performance system speed: Commercial and Industrial: — 5ns Clock-to-Data Access (100MHz) — 6ns Clock-to-Data Access (83MHz) — 7ns Clock-to-Data Access (66MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC32K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Operates with a single 3.3V power supply (+10/-5%) Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP). Description The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM organized as 32K x 32 with full support of the Pentium™ and PowerPC™ processor interfaces. The pipelined burst architecture provides costeffective 3-1-1-1 secondary cache performance for processors up to 100 MHz. The IDT71V432 CacheRAM contains write, data, address, and control registers. Internal logic allows the CacheRAM to generate a selftimed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V432 can provide four cycles of data for a single address presented to the CacheRAM. An internal burst address counter accepts the first cycle address from the pro.


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