DatasheetsPDF.com

IDT71V546S Datasheet

Part Number IDT71V546S
Manufacturers IDT
Logo IDT
Description 3.3V Synchronous SRAM
Datasheet IDT71V546S DatasheetIDT71V546S Datasheet (PDF)

128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined Outputs Features ◆ 128K x 36 memory configuration, pipelined outputs ◆ Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized registered outputs eliminate the need to control OE ◆ Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD B.

  IDT71V546S   IDT71V546S






Part Number IDT71V546S
Manufacturers Renesas
Logo Renesas
Description Synchronous SRAM
Datasheet IDT71V546S DatasheetIDT71V546S Datasheet (PDF)

128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined Outputs Features ◆ 128K x 36 memory configuration, pipelined outputs ◆ Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized registered outputs eliminate the need to control OE ◆ Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD B.

  IDT71V546S   IDT71V546S







3.3V Synchronous SRAM

128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined Outputs Features ◆ 128K x 36 memory configuration, pipelined outputs ◆ Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized registered outputs eliminate the need to control OE ◆ Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ 4-word burst capability (interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ Single 3.3V power supply (±5%) ◆ Packaged in a JEDEC standard 100-pin TQFP package ◆ Green parts available, see Ordering Information 128K x 36 BIT MEMORY ARRAY Address Control DI DO Input Reg.


2019-04-07 : IDT54FCT373AT    IDT74LVCH162373A    IDT74ALVCH32245    MGBR20L60    IDT74ALVCHR162245    IDT74LVC16827A    IDT71T75902    IDT71V2546XS    IDT71V2556S    IDT71V2546S   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)