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IDT72V3693 Datasheet

Part Number IDT72V3693
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3 VOLT CMOS SyncFIFO
Datasheet IDT72V3693 DatasheetIDT72V3693 Datasheet (PDF)

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36 IDT72V3683 IDT72V3693 IDT72V36103 FEATURES • • • • • • • Memory storage capacity: IDT72V3683 – 16,384 x 36 IDT72V3693 – 32,768 x 36 IDT72V36103 – 65,536 x 36 Clock frequencies up to 100 MHz (6.5 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; ea.

  IDT72V3693   IDT72V3693






Part Number IDT72V3696
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3 VOLT CMOS TRIPLE BUS SyncFIFO
Datasheet IDT72V3693 DatasheetIDT72V3696 Datasheet (PDF)

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2 IDT72V3686 IDT72V3696 IDT72V36106 • • • • • • • FEATURES • • • • • • Memory storage capacity: IDT72V3686 – 16,384 x 36 x 2 IDT72V3696 – 32,768 x 36 x 2 IDT72V36106 – 65,536 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 18-bit (wor.

  IDT72V3693   IDT72V3693







Part Number IDT72V3694
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3 VOLT CMOS SyncBiFIFO
Datasheet IDT72V3693 DatasheetIDT72V3694 Datasheet (PDF)

3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 IDT72V3684 32,768 x 36 x 2 IDT72V3694 65,536 x 36 x 2 IDT72V36104 FEATURES • • • • • • • • • • • • Memory storage capacity: IDT72V3684 – 16,384 x 36 x 2 IDT72V3694 – 32,768 x 36 x 2 IDT72V36104 – 65,536 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent clocked FIFOs buffering data in opposite directions Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through T.

  IDT72V3693   IDT72V3693







Part Number IDT72V3692
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3 VOLT CMOS SyncBiFIFO
Datasheet IDT72V3693 DatasheetIDT72V3692 Datasheet (PDF)

3.3 VOLT CMOS SyncBiFIFOTM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2 IDT72V3682 IDT72V3692 IDT72V36102 FEATURES • • • • • Memory storage capacity: IDT72V3682 – 16,384 x 36 x 2 IDT72V3692 – 32,768 x 36 x 2 IDT72V36102 – 65,536 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in.

  IDT72V3693   IDT72V3693







Part Number IDT72V3690
Manufacturers Renesas
Logo Renesas
Description 3.3V HIGH-DENSITY 36-BIT FIFO
Datasheet IDT72V3693 DatasheetIDT72V3690 Datasheet (PDF)

3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 IDT72V3640, IDT72V3650 4,096 x 36, 8,192 x 36 IDT72V3660, IDT72V3670 16,384 x 36, 32,768 x 36 IDT72V3680, IDT72V3690 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • Choose among the following memory organizations:Commercial IDT72V3640 ⎯ 1,024 x 36 IDT72V3650 ⎯ 2,048 x 36 IDT72V3660 ⎯ 4,096 x 36 IDT72V3670 ⎯ 8,192 x 36 IDT72V3680 ⎯ 16,384 x 36 IDT72V3690 ⎯ 32,768 x 36 • Up to 166 MHz.

  IDT72V3693   IDT72V3693







3.3 VOLT CMOS SyncFIFO

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36 IDT72V3683 IDT72V3693 IDT72V36103 FEATURES • • • • • • • Memory storage capacity: IDT72V3683 – 16,384 x 36 IDT72V3693 – 32,768 x 36 IDT72V36103 – 65,536 x 36 Clock frequencies up to 100 MHz (6.5 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) • • • • • • • • • • Big- or Little-Endian format for word and byte bus sizes Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin compatible with the lower density parts, IDT72V3623/ 72V3633/72V3643/72V3653/72V3663/72V3673 Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Port-A Control Logic CLKA CSA W/RA ENA MBA RS1 RS2 PRS BusMatching Input Register Output Re.


2011-06-26 : JSL    L431L    IDT72V36102    IDT72V3682    IDT72V3692    IDT72V36103    IDT72V3683    IDT72V3693    IDT72V36104    IDT72V3684   


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