FEATURES:
• Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes
• 1Ons typical d...
FEATURES:
Equivalent to ALS speeds and output drive over full temperature and
voltage supply extremes
1Ons typical data to output delay IOL = 14mA over full military temperature range
CMOS power levels (5/lW typo static) Both
CMOS and TTL output compatible Substantially lower input current levels than ALS (5J1.A max.) Octal transparent latch with enable 100% product assurance screening to MIL-STD-883, Class B
is available JEDEC standard pinout for DIP and LCC
DESCRIPTION:
The IDT54/74AHCT573 are 8-bit latches built using advanced CEMOS'·, a dual metal
CMOS technology. This octal latch has 3-state outputs and is intended for bus-oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
PIN CONFIGURATIONS
OE
Do 0,
O2 03
D...
