IDT74ALVCH162721

IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH162721 FEATURES: 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.635mm pitch SSOP, 0.50mm pitch TSSOP, www.DataSheet4U.com and 0.40mm pitch TVSOP packages – Extended commercial range of – 40°C to + 85°C – VCC = 3.3V ± 0.3V, Normal Range – VCC = 2.7V to 3.6V, Extended Range – VCC = 2.5V ± 0.2V – CMOS power levels (0.4µ W typ. static) – Rail-to-Rail output swing for increased noise margin Drive Features for ALVCH162721: – Balanced Output Drivers: ±12mA – Low switching noise – – – DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the highimpedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE...