IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT I...
IDT74ALVCH16901 3.3V
CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
3.3V
CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/ CHECKERS AND BUS-HOLD
0.5 MICRON
CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range www.DataSheet4U.com VCC = 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in TSSOP package
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
High Output Drivers: ±24mA Suitable for heavy loads
APPLICATIONS:
3.3V high speed systems 3.3V and lower
voltage computing systems
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. The ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL ...