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IDTCV109E Datasheet

Part Number IDTCV109E
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
Datasheet IDTCV109E DatasheetIDTCV109E Datasheet (PDF)

www.DataSheet4U.com IDTCV109E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR FOR DESKTOP PC PLATFORMS IDTCV109E FEATURES: • • • • • • • • • • • DESCRIPTION: 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.1G Support index block read/write, single cycle index block read Programm.

  IDTCV109E   IDTCV109E






CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

www.DataSheet4U.com IDTCV109E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR FOR DESKTOP PC PLATFORMS IDTCV109E FEATURES: • • • • • • • • • • • DESCRIPTION: 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.1G Support index block read/write, single cycle index block read Programmable REF, 3V66, PCI, 48MHz I/O drive strength Programmable 3V66 and PCI Skew Available in SSOP package IDTCV109E is a 48 pin clock generation device for desktop PC platforms. This chip incorporates four PLLs to allow independent generation of CPU, AGP/ PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, providing high accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread Spectrum selection. KEY SPECIFICATION: • • • • CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.com PLL1 SSC EasyN Programming CPU CLK Output Buffers CPU[1:0] ee DataSh X1.


2006-10-11 : CY7C344    DM7450    DM7451    ICS9160-03    ICS9161A    ICS9169A-70    ICS9169C-231    ICS9169C-232    ICS9169C-27    ICS9169C-271   


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