IS43R83200B

IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM AUGUST 2010 FEATURES: Vdd =Vddq = 2.5V+0.2V (-5, -6, -75) Double data rate architecture; two data transfers per clock cycle. Bidirectional , data strobe (DQS) is transmitted/ received with data Differential clock input (CLK and /CLK) DLL aligns DQ and DQS transitions with CLK transitions edges of DQS Commands entered on each positive CLK edge; Data and data mask referenced to both edges of DQS 4 bank operation controlled by BA0 , BA1 (Bank Address) /CAS latency -2.0 / 2.5 / 3.0 (programmable) ; Burst length -2 / 4 / 8 (programmable) Burst type -Sequential / Interleave (programmable) Auto precharge/ All bank precharge controlled by A10 8192 refresh cycles / 64ms (4 banks concurrent refresh) Auto refresh and Self refresh Row address A0-12 / Column address A0-9(x8)/ A0-8(x16) SSTL_2 Interface Package: 66-pin TSOP II (x8 and...