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IS61NVP102418B Datasheet

Part Number IS61NVP102418B
Manufacturers ISSI
Logo ISSI
Description 18Mb STATE BUS SYNCHRONOUS SRAM
Datasheet IS61NVP102418B DatasheetIS61NVP102418B Datasheet (PDF)

IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Thre.

  IS61NVP102418B   IS61NVP102418B






Part Number IS61NVP102418
Manufacturers ISSI
Logo ISSI
Description (IS61NVPxxxxx) STATE BUS SRAM
Datasheet IS61NVP102418B DatasheetIS61NVP102418 Datasheet (PDF)

IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES www.DataSheet4U.com ISSI JULY 2006 ® DESCRIPTION The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M.

  IS61NVP102418B   IS61NVP102418B







18Mb STATE BUS SYNCHRONOUS SRAM

IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • /CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages • Power supply: NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%) • JTAG Boundary Scan for BGA packages • Commercial, Industrial and Automotive (x36) temperature support • Lead-free available • For leaded option, please contact ISSI. DESCRIPTION The 18Meg product family features high-speed, lowpower synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 512K words by 36 bits and 1024K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read.


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