IS61VPS204818A

IS61vPS102436A IS61lPS102436A IS61vPS204818A IS61lPS204818A 1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM JUNE 2010 FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth ex- pansion and address pipelining Common data inputs and data outputs Auto Power-down during deselect Single cycle deselect Snooze MODE for reduced-power standby Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% JEDEC 100-Pin TQFP and 165-ball PBGA packages Lead-free available FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency DESCRIPTION The  ISSI IS61LPS/VPS102436A and IS61LPS/VPS 204818A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS102436A is organized as 1,048,476 words by 36 bits.The IS61LPS/VPS204818A is organized as 2M-word by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positiveedge-triggered single clock input. Write cycles are internally self-timed and are initiated by...