K4T51163QB

512Mb B-die DDR2 SDRAM DDR2 SDRAM 512Mb B-die DDR2 SDRAM Specification Version 1.4 February 2005 Page 1 of 29 Rev. 1.4 Feb. 2005 512Mb B-die DDR2 SDRAM Contents DDR2 SDRAM 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page 2 of 29 Rev. 1.4 Feb. 2005 512Mb B-die DDR2 SDRAM 0. Ordering Information Organization 128Mx4 K4T51043QB-ZCD5 K4T51083QB-GCD5 64Mx8 K4T51083QB-ZCD5 K4T51163QB-GCD5 32Mx16 K4T51163QB-ZCD5 Note : Speed bin is in order of CL-tRCD-tRP K4T51163QB-ZCCC Lead-Free K4T51083QB-ZCCC K4T51163QB-GCCC Lead-Free Leaded K4T51043QB-ZCCC K4T51083QB-GCCC Lead-Free Leaded DDR2-533 4-4-4 K4T51043QB-GCD5 DDR2-400 3-3-3 K4T51043QB-GCCC Package Leaded DDR2 SDRAM 1.Key Features Speed CAS Latency tRCD(min) tRP(min) tRC(min) DDR2-533 4-4-4 4 15 15 55 DDR2-400 3-3-3 3 15 15 55 Units tCK ns ns ns JEDEC standard 1.8V ± 0.1V Power Supply VDDQ = 1.8V ± 0.1V 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin 4 Banks Posted CAS Programmable CAS Latency: 3, 4, 5 Programmable Additive Latency: 0, 1 , 2 , 3 and 4 Write Latency(WL) = Read Latency(RL) -1 Burst Length: 4 , 8(Interleave/nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature...