K4X56163PE-LFG

K4X56163PE-L(F)G 16M x16 Mobile DDR SDRAM FEATURES Mobile-DDR SDRAM 1.8V power supply, 1.8V I/O power Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and CK) MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 array ) - Internal Temperature Compensated Self Refresh - Driver strength ( 1, 1/2, 1/4, 1/8 ) All inputs except data & DM are sampled at the positive going edge of the system clock(CK). Data I/O transactions on both edges of data strobe, DM for masking. Edge aligned data output, center aligned data input. No DLL; CK to DQS is not synchronized. LDM/UDM for write masking only. 7.8us auto refresh duty cycle. CSP package. Operating Frequency DDR200 Speed @CL3 *CL : CAS Latency DDR133 66Mhz 100Mhz Column address configuration Organization 16Mx16 DM is internally loaded to match DQ and DQS identically. Row Address A0 ~ A12 Column Address A0-A8 1 March 2004 K4X56163PE-L(F)G Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A e B C D A B C D E F G D/2 H J K E E/2 Ball Name 8 7 6 5 4 3 2 1 1 VSS VDDQ VSSQ VDDQ VSSQ VSS CKE A9 A6 VSS Mobile-DDR SDRAM < Top View*2 > 60Ball(6x10) CSP 2 DQ15 DQ13 DQ11 DQ9 UDQS UDM CK A11 A7 A4 3 VSSQ DQ14 DQ12 DQ10 DQ8 N.C. CK A12 A8 A5 7 VDDQ DQ1 DQ3 DQ5 DQ7 N.C. WE CS A10/AP A2 8 DQ0 DQ...