CMOS SRAM. KM641003B Datasheet
|Total Page||8 Pages|
256Kx4 Bit (with OE) High Speed Static RAM(5.0V Operating), Revolutionary Pin out.
Initial release with Design Target.
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary
2.2. Delete L-version.
2.3. Delete Data Retention Characteristics and Waveform.
2.4. Delete Industrial Temperature Range Part
2.5. Delete TSOP2 Package
2.6. Add Capacitive load of the test environment in A.C test load
2.7. Change D.C characteristics
Apr. 1st, 1997
Jun. 1st, 1997
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers.
256K x 4 Bit (with OE)High-Speed CMOS Static RAM
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL) : 50 mA(Max.)
(CMOS) : 10 mA(Max.)
Operating KM641003B - 8 : 150 mA(Max.)
KM641003B - 10 : 145 mA(Max.)
KM641003B - 12 : 140 mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM641003BJ : 32-SOJ-400
The KM641003B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
KM641003B uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG ′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM641003B is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION (Top View)
FUNCTIONAL BLOCK DIAGRAM
A3 Memory Array
I/O1 ~ I/O4
I/O Circuit &
A8 A9 A10 A11 A12 A13 A14 A15 A16A17
A0 - A17
I/O1 ~ I/O4
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