PREAMPLIFIER. L6316 Datasheet

L6316 Datasheet PDF

Part L6316
Description 4-CHANNEL LOW POWER PREAMPLIFIER
Feature L6316; www.DataSheet4U.com L6316 4-CHANNEL LOW POWER PREAMPLIFIER DATA BRIEF 1 ■ ■ FEATURES Dual Power S.
Manufacture STMicroelectronics
Datasheet
Download L6316 Datasheet




L6316
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L6316
4-CHANNEL LOW POWER PREAMPLIFIER
DATA BRIEF
1 FEATURES
Dual Power Supplies of +5V, 10% and -3v, 6%
Low Power consumption; 980 mW @ 800Mb/s
(Single Head 100% Write mode duty cycle,
Random pattern, Iw = 40mA, Max Ovs).
Flip Chip package.L6316
Differential Voltage Bias / Voltage Sense
architecture. Current Bias available
Programmable read input differential
impedance.
Selectable read path bandwidth from 200 to
>600 MHz (Rmr=40). (Parameter dependent
on interconnect)
Selectable LF corner (1, 2.5, 3.5 or 5.5 MHz with
RMR=40).
Noise Figure of merit; 2.2 dB (Rmr=40)
MR bias voltage programmable from 70 to 225
mV nom. (5 bits) (7.2mA max).
MR bias current programmable from 0.65 to
7.2 mA nom. (5 bits) (225mV max).
Read input stage optimized for MR resistance
from 20 to 70 Ohm.
Programmable read voltage gain of 37, 40, 43,
46 dB Rmr = 40, Rload = 100
Fully Differential write driver: Programmable
overshoot amplitude (3bits) and duration (2bits).
Write current rise/fall time with custom head and
interconnect model 140 pS at 40 mA (10% to
90%) (Steady state to steady state)
Write current amplitude programmable (5 bits) 0
to 62 mA (0-pk).
Bi-directional 16-bit serial interface 2.5V and
3.3V CMOS compatible.
2-pin (RXW and TFI), 2 bits mode selection
(WAKE, ENTFI).
All control signals are 2.5 & 3.3V CMOS
compatible.
Analog buffered head voltage ABHV (gain of 5)
Automatic digital MR resistance measurement
(7 bits).
Read head open detection, Read head shorted
detection.
Write head open or shorted to ground, Writer to
Reader short, write data frequency too low
detection.
SAFEDETECT method for write fault detection.
Figure 1. Package
Flip Chip
Table 1. Order Codes
Part Number
L6316
Package
Flip Chip
Low VCC or VEE supply & die over temperature
detect, Analog Temperature Measurement.
Fast write-to-read recovery 150nS (max) (same
head).
Head-to-head switch in read mode 1.5us (nom).
Zero MR bias, very low power (43mW) idle mode
with fast recovery to read mode 1.5us (nom).
MR bias switching without overshoot for head
protection.
Read-to-Write switching 50nS (max) (same
head).
ESD diodes for MR head protection
2 DESCRIPTION
The L6316 is a BICMOS Silicon Germanium inte-
grated circuit differential preamplifier. It is de-
signed for use with four-terminal MR read and in-
ductive write heads. In read mode, the device
consists of a fully differential amplifier, offering;
voltage or current bias, voltage-sense input, pro-
grammable input impedance, low noise and high
bandwidth. In write mode, it includes fast current
switching differential write drivers, which support
data rates up to 1200 Mb/s.
This preamplifier provides programmable read
voltage or current bias and write current (5 bit
DACs for the read bias and for the write current),
fault detection circuitry and servo track writing fea-
tures. Read amplifier gain, low corner frequency,
and write current wave shape are adjustable. The
amplitude and duration of the overshoot are sepa-
rately programmable through a 16-bit bi-direction-
al serial interface (SEN, SDATA, and SCLK). The
device operates from +5V and -3V supplies.
September 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
Rev. 1
1/6



L6316
L6316
Figure 2. Preamplifier Block Diagram
VCC (+5V)
VGND (0V)
VEE (-3V)
WDX
WDY
FLT
PREDRIVER
FAULT PROCESSOR
Low supply detection,
Open/short heads,
Low write frequency,
High temperature
WRITE
DRIVERS
SDATA
SCLK
SEN
SERIAL INTERFACE
CONTROL
RXW
TFI
3v
HEAD SELECTION
3v &
MODE CONTROL
RDX
RDY
Gain boost
Low pass filter
High pass
filter
L6316
Vmr, Iw
RW enable
head select
ABHV,
MR meas,
TEMP meas
Temperature
monitoring
WRITE
DAC
READ
BIAS
DAC
MR
READ
INPUT
STAGES
VREF
Rin DAC
HW0X
HW0Y
HW1X
HW1Y
HW2X
HW2Y
HW3X
HW3Y
HR0X
HR0Y
HR1X
HR1Y
HR2X
HR2Y
HR3X
HR3Y
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L6316
Figure 3. Flip Chip Pinout Diagram - BUMPS DOWN
Note: Minimum pad pitch = 204 um and pad opening (octagonal) = 70 um
Bump Sequence (see next table for coordinates)
TF VEE GND VCC
HR3Y HR3X
L6316
SDEN
WDY
WDX
SCLK
RDX
RDY
SDATA
RXW
FLT
HW3Y
HW3X
HW2X
0,0 HW2Y
HW1Y
HW1X
HW0X
HW0Y
HR2X
HR2Y
HR1Y
HR1X
VEE GND VREF VCC
HR0Y HR0X
Die dimensions:
Minimum distance between pads opening center to center:
Wafer thickness:
Bump height:
Bump diameter:
Die center misalignment w.r.t original die center after cut:
Bump material if eutectic:
Bump material if lead free:
X = 2192 ±20 um
Y = 2686 ±20 um
204um
500 ±20 um
90 ±15 um
120 ±15 um
38 um
63% Tin, 37% Lead
96% Tin, 3.5% Silver, 0.5% Copper
Note: VREF PAD can be left floating or grounded. DO NOT CONNECT IT ANYWHERE ELSE.
3/6







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