MachXO Family Data Sheet
Version 02.3_4W February 2007
MachXO Family Data Sheet Introduction
April 2006
Data Sheet
F...
MachXO Family Data Sheet
Version 02.3_4W February 2007
MachXO Family Data Sheet Introduction
April 2006
Data Sheet
Features
■ Non-volatile, Infinitely Reconfigurable Instant-on – powers up in microseconds Single chip, no external configuration memory required Excellent design security, no bit stream to intercept Reconfigure SRAM based logic in milliseconds SRAM and non-volatile memory programmable through JTAG port Supports background programming of non-volatile memory
■ Sleep Mode Allows up to 100x static current reduction
■ TransFR™ Reconfiguration (TFR) In-field logic update while system operates
■ High I/O to Logic Density 256 to 2280 LUT4s 73 to 271 I/Os with extensive package options Density migration supported Lead free/RoHS compliant packaging
■ Embedded and Distributed Memory Up to 27.6 Kbits sysMEM™ Embedded Block RAM Up to 7.5 Kbits distributed RAM Dedicated FIFO control logic
■ Flexible I/O Buffer Programmable sysIO™ buffer supports wide range of interfaces: − LV
CMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL − PCI − LVDS, Bus-LVDS, LVPECL, RSDS
■ sysCLOCK™ PLLs Up to two analog PLLs per device Clock multiply, divide, and phase shifting
■ System Level Support IEEE Standard 1149.1 Boundary Scan Onboard oscillator Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply IEEE 1532 compliant in-system programming
Introduction
The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity...