Chip Multilayer Delay Lines
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Description
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N91E7.pdf 03.5.13
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Chip Multilayer Delay Lines
Chip Multilayer Delay Lines
1
3.2±0.2
1.1±0.2
1.60±0.2 0.25+0.1/-0.15 0.5±0.1
This Delay Line was developed by applying ceramic
(3) (2) (1)
multilayering and hole technology. It consists of copper line and low dielectric constant material and incorporates metal shields. LDH series are very small
(4) (8)
(5) (6) (7) 0.25+0.1/-0.15
and made for use at high frequencies.
0.35±0.2 0.45±0.15
s Features
(1)(3)(5)(7) : NC (2)(6) : GND (4)(8) : IN/OUT
1. High stability at high frequency (2GHz)
0.5±0.1
1.0±0.1
(in mm)
2. Small, thin and light, utilizing multilayer construction
m3. Metal shield is built inside chip.
4. Reflow solderable
o5. Supplied on tape
Sheet4U.c0.6±0.1
.DataDirectional
Input Mark
(1) (2) (3) (8) (4)
(7) (6) (5)
0.4±0.2
4.5±0.2
3.2±0.2
2.2±0.1 0.3±0.2 0.1±0.1
...
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