LF2247

LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM DESCRIPTION The LF2247 consists of an array of four 11 x 10-bit registered multipliers followed by a summer and a 25-bit accumulator. The LF2247 provides a coefficient register file containing four 32 x 11-bit registers which are capable of storing 32 different sets of filter coefficients for the multiplier array. All multiplier data inputs are user accessible and can be updated every clock cycle with either fractional or integer two’s complement data. The pipelined architecture has fully registered input and output ports and an asynchronous three-state output enable control to simplify the design of complex systems. The pipeline latency for all inputs is five clock cycles. A 25-bit accumulator path allows cumulative word growth which may be internally rounded to 16 bits. Output data is updated every clock cycle and may be held under user control. The data inputs/outputs and control inputs are registered on the rising edge of CLK. The Serial Data In signal, SDIN, is registered on the FEATURES u 66 MHz Data Input and Computation Rate u Four 11 x 10-bit Multipliers with Individual Data and Coefficient Inputs and a 25-bit Accumulator u Four 32 x 11-bit Serially Loadable Coefficient Registers u Fractional or Integer Two’s Complement Operands u Package Styles Available: 84-pin PLCC, J-Lead 100-pin PQFP 1 2 3 4 5 6 LF2247 BLOCK DIAGRAM ENBA 5 A4-0 C...