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LM98640QML-SP Datasheet

Part Number LM98640QML-SP
Manufacturers Texas Instruments
Logo Texas Instruments
Description 40-MSPS Analog Front-End
Datasheet LM98640QML-SP DatasheetLM98640QML-SP Datasheet (PDF)

Product Folder Order Now Technical Documents Tools & Software Support & Community LM98640QML-SP SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output 1 Features •1 Radiation Hardened – TID 100 krad(Si) – Single Event Latch-Up (SEL) Immune to LET = 120 MeV-cm2/mg – Single Event Functional Interrupt (SEFI) Free to 120 MeV-cm2/mg – SMD 5962R1820301VXC • ADC Resolution: 14-Bit • ADC Sampling R.

  LM98640QML-SP   LM98640QML-SP






40-MSPS Analog Front-End

Product Folder Order Now Technical Documents Tools & Software Support & Community LM98640QML-SP SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output 1 Features •1 Radiation Hardened – TID 100 krad(Si) – Single Event Latch-Up (SEL) Immune to LET = 120 MeV-cm2/mg – Single Event Functional Interrupt (SEFI) Free to 120 MeV-cm2/mg – SMD 5962R1820301VXC • ADC Resolution: 14-Bit • ADC Sampling Rate: 5 MSPS to 40 MSPS • Input Level: 2.85 V • Supply Voltages 3.3 V and 1.8 V (Nominal) – 125 mW per Channel at 15 MSPS – 178 mW per Channel at 40 MSPS • CDS or S/H Processing for CCD or CIS Sensors – CDS or S/H Gain 0 dB or 6 dB • Programmable Analog Gain for Each Channel – 256 Steps; Range –3 dB to 18 dB • Programmable Analog Offset Correction – Fine and Coarse DAC Resolution ±8 Bits – Fine DAC Range ±5 mV – Coarse DAC Range ±250 mV • Programmable Input Clamp Voltage • Programmable Sample Edge: 1/64th Pixel Period • INL at 15 MHz: ±3.5 LSB • Noise Floor: –79 dB • Crosstalk: –80 dB • Operating Temp: –55°C to 125°C VSS33 VDD33 VCOM1 VREFT1 VREFB1 IBIAS VREFBG VDD18 VSS18 INCLK+ INCLK- OS1OS1+ VCLP OS2+ OS2- DLL ATG 64 CDAC1[ COARSE 8:0] 9 DAC FDAC1[ 8:0] 9 FINE DAC Input Bias/ Clamping -CDS +S/H VCLP Reference DAC VCLP 5 Control[4:0] Input Bias/ Clamping +CDS - S/H FDAC2[ FINE 8:0] 9 DAC CDAC2[ COARSE 8:0] 9 DAC INTERNAL REFERENCE VBG PGA1[7:0] 8 PGA 14 Bit .


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