LMC568 Low Power Phase-Locked Loop
May 1999
LMC568 Low Power Phase-Locked Loop
General Description
The LMC568 is an am...
LMC568 Low Power Phase-Locked Loop
May 1999
LMC568 Low Power Phase-Locked Loop
General Description
The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and a carrier detect output. LM
CMOS™ technology is employed for high performance with low power consumption. The VCO has a linearized control range of ± 30% to allow demodulation of FM and FSK signals. Carrier detect is indicated when the PLL is locked to an input signal greater than 26 mVrms. LMC568 applications include FM SCA and TV second audio program decoders, FSK data demodulators, and voice pagers.
Features
n n n n n n Demodulates ± 15% deviation FM/FSK signals Carrier Detect Output with hysteresis Operation to 500 kHz input frequency Low THD — 0.5% typ. for ± 10% deviation 2V to 9V supply
voltage range Low supply current drain
Typical Application
(100 kHz input frequency, refer to notes pg. 3)
DS009135-1
Order Number LMC568CM or LMC568CN See NS Package Number M08A or N08E
LM
CMOS™ is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS009135
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input
Voltage, Pin 3 Supply
Voltage, Pin 4 Output
Voltage, Pin 8
Voltage at All Other Pins Output Current, Pin 8 Package Dissipation Operating Temperature Range (...