LMK05028

Product Folder Order Now Technical Documents Tools & Software Support & Community LMK05028 SNAS724A – FEBRUARY 2018 – REVISED APRIL 2018 LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM 1 Features 1 Two Independent PLL Channels Featuring: – Jitter: 150-fs RMS for Outputs ≥ 100 MHz – Phase Noise: –112 dBc/Hz at 100-Hz Offset for 122.88 MHz – Hitless Switching: 50-ps Phase Transient With Phase Cancellation – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO – Any Input to Any Output Frequency Translation Four Reference Clock Inputs – Priority-Based Input Selection – Digital Holdover on Loss of Reference Eight Clock Outputs With Programmable Drivers – Up to Six Different Output Frequencies – AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V or 2.5-V LVCMOS Output Formats EEPROM/ROM for Custom Clocks on Power-Up(2) Flexible Configuration Options – 1 Hz (1 PPS) to 750 MHz on Input and Output – XO: 10 to 100 MHz, TCXO: 10 to 54 MHz – DCO Mode: < 1 ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave) – Zero Delay for Deterministic Phase Offset – Robust Clock Monitoring and Status – I2C or SPI Interface Excellent Power Supply Noise Rejection (PSNR) 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs Industrial Temperature Range: –40°C to +85°C 2 Applications SyncE (G.8262), SONET/SDH (Stratum 3/3E, G.813, GR-1244, GR-253), IEEE 1588 PTP Slave Clock, or Optical Trans...