LP62S1024A-I Series
Preliminary
Features
n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: V...
LP62S1024A-I Series
Preliminary
Features
n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30mA(max.) (55NS)40mA(max.) Standby: 5uA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention
voltage: 2V (min.) n Available in 32-pin TSOP, TSSOP (8X13.4mm) packages
128K X 8 BIT LOW
VOLTAGE CMOS SRAM
General Description
The LP62S1024A-I is a low operating current 1,048,576bit static random access memory organized as 131,072 words by 8 bits and operates on a low power
voltage: 2.7V to 3.6V. It is built using AMIC's high performance
CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply
voltage as low as 2V.
n TSOP/TSSOP
16
1
LP62S1024AV-I (LP62S1024AX-I)
17 32
Pin No. Pin Name Pin No. Pin Name
1 A11 17 A3
2 A9 18 A2
3 A8 19 A1
4 A13 20 A0
5 WE 21 I/O1
6 CE2 22 I/O 2
7 A15 23 I/O 3
8 VCC 24 GND
9 NC 25 I/O4
10 A16 26 I/O5
11 A14 27 I/O6
12 A12 28 I/O 7
13 A7 29 I/O 8
14 A6 30 CE1
15 A5 31 A10
16 A4 32 OE
PRELIMINARY
(August, 2001, Version 0.1)
1
AMIC Technology, In...
