LP62S16128B-I Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
n Operating voltage: 2.7V to 3.6V n Access times: 55/7...
LP62S16128B-I Series
128K X 16 BIT LOW
VOLTAGE CMOS SRAM
Features
n Operating
voltage: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 55ns 40mA (max.) 70ns 35mA (max.) Standby: 10µA (max.) n n n n n Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Data retention
voltage: 2V (min.) Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm) packages
General Description
The LP62S16128B-I is a low operating current 2,097,152bit static random access memory organized as 131,072 words by 16 bits and operates on low power
voltage from 2.7V to 3.6V. It is built using AMIC's high performance
CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply
voltage as low as 2V.
Pin Configurations
n TSOP n CSP (Chip Size Package) 48-pin Top View
A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12
1 2 3 4
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE HB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
1 A B C D E F G H LB I/O9 I/O10 GND VCC I/O15 I/O16 NC
2 OE HB I/O11 I/O12 I/O13 I/O14 NC A8
3 A0...