M15F5121632A

ESMT DDR3 SDRAM (Preliminary) Feature Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM Data Integrity ˗ Auto Refresh and Self Refresh Modes Power Saving Mode ˗ Partial Array Self Refresh(PASR) ˗ Power Down Mode Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) Signal Synchronization M15F5121632A 4M x 16 Bit x 8 Banks DDR3 SDRAM ˗ Write Leveling via MR settings ˗ Read Leveling via MPR Programmable Functions ˗ CAS Latency (5/6/7/8/9/10/11/12/13) ˗ CAS Write Latency (5/6/7/8/9) ˗ Additive Latency (0/CL-1/CL-2) ˗ Write Recovery Time (5/6/7/8/10/12/14/16) ˗ Burst Type (Sequential/Interleaved) ˗ Burst Length (BL8/BC4/BC4 or 8 on the fly) ˗ Self Refresh Temperature Range(Normal/Extended) ...