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M15T1G1664A Datasheet

Part Number M15T1G1664A
Manufacturers ESMT
Logo ESMT
Description DDR3 SDRAM
Datasheet M15T1G1664A DatasheetM15T1G1664A Datasheet (PDF)

ESMT DDR3(L) SDRAM Feature Interface and Power Supply SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) SSTL_15: VDD/VDDQ = 1.5V(±0.075V) JEDEC DDR3(L) Compliant 8n Prefetch Architecture Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) Double-data rate on DQs, DQS and DM Data Integrity Auto Refresh and Self Refresh Modes Power Saving Mode Partial Array Self Refresh(PASR) Power Down Mode Signal Integrity Configurable DS for system compatibility Configurable On-Die Termination ZQ Calibration for D.

  M15T1G1664A   M15T1G1664A






DDR3 SDRAM

ESMT DDR3(L) SDRAM Feature Interface and Power Supply SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) SSTL_15: VDD/VDDQ = 1.5V(±0.075V) JEDEC DDR3(L) Compliant 8n Prefetch Architecture Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) Double-data rate on DQs, DQS and DM Data Integrity Auto Refresh and Self Refresh Modes Power Saving Mode Partial Array Self Refresh(PASR) Power Down Mode Signal Integrity Configurable DS for system compatibility Configurable On-Die Termination ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15T1G1664A (2C) 8M x 16 Bit x 8 Banks DDR3(L) SDRAM Signal Synchronization Write Leveling via MR settings Read Leveling via MPR Programmable Functions CAS Latency (5/6/7/8/9/10/11/12/13) CAS Write Latency (5/6/7/8/9) Additive Latency (0/CL-1/CL-2) Write Recovery Time (5/6/7/8/10/12/14/16) Burst Type (Sequential/Interleaved) Burst Length (BL8/BC4/BC4 or 8 on the fly) Self Refresh Temperature Range(Normal/Extended) Output Driver Imped.


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