SDRAM. M53D5121632A Datasheet

M53D5121632A Datasheet PDF


Part M53D5121632A
Description Mobile DDR SDRAM
Feature ESMT Mobile DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two .
Manufacture ESMT
Datasheet
Download M53D5121632A Datasheet


ESMT Mobile DDR SDRAM Features JEDEC Standard Internal pipel M53D5121632A Datasheet




M53D5121632A
ESMT
Mobile DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
- Deep Power Down (DPD) Mode
M53D5121632A
8M x16 Bit x 4 Banks
Mobile DDR SDRAM
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
VDD/VDDQ = 1.7V ~ 1.95V
Auto & Self refresh
7.8us refresh interval (64ms refresh period, 8K cycle)
LVCMOS-compatible inputs
Ordering Information
Product ID
M53D5121632A -5BG
M53D5121632A -6BG
M53D5121632A -7.5BG
Max Freq.
200MHz
166MHz
133MHz
VDD
1.8V
Package
Comments
60 ball BGA
Pb-free
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS
DM
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2016
Revision : 1.0
1/47



M53D5121632A
ESMT
M53D5121632A
BALL CONFIGURATION (TOP VIEW)
(BGA60, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)
1
A VSSQ
2
DQ15
3
VSS
789
VDD DQ0 VDDQ
B DQ14 VDDQ DQ13
DQ2 VSSQ DQ1
C DQ12 VSSQ DQ11
DQ4 VDDQ DQ3
D DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
E DQ8 VSSQ UDQS
LDQS VDDQ DQ7
F NC VSS UDM
LDM VDD NC
G CLK CLK
WE CAS
H A12 CKE
J A11 A9
K A8 A7
L A6 A5
M A4 VSS
RAS CS
BA1 BA0
A0 A10/AP
A2 A1
VDD
A3
Ball Description
Ball Name
Function
A0~A12,
BA0~BA1
Address inputs
- Row address A0~A12
- Column address A0~A9
A10/AP : AUTO Precharge
BA0~BA1 : Bank selects (4 Banks)
DQ0~DQ15 Data-in/Data-out
RAS
CAS
WE
VSS
VDD
LDQS, UDQS
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe.
LDQS corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on DQ8~DQ15
Ball Name
Function
LDM, UDM
DM is an input mask signal for write data.
LDM corresponds to the data on DQ0~DQ7;
UDM correspond to the data on DQ8~DQ15
CLK, CLK
CKE
CS
VDDQ
VSSQ
NC
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2016
Revision : 1.0
2/47






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