MB84VD2119xA

( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50202-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M ( × 8/ × 16) FLASH MEMORY & 4M ( × 8/ × 16) STATIC RAM MB84VD2118XA-85/MB84VD2119XA-85 s FEATURES Power supply voltage of 2.7 V to 3.6 V High performance 85 ns maximum access time Operating Temperature −25 °C to +85 °C Package 69-ball FBGA, 56-pin TSOP(I) (Continued) s PRODUCT LINE UP Flash Memory Ordering Part No. VCCf*, VCCs* = 3.0 V +0.6 V −0.3 V SRAM MB84VD2118XA-85/MB84VD2119XA-85 85 85 35 85 85 45 Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) *: Both VCCf and VCCs must be in recommended operation range when either part is being accessed. s PACKAGES 69-ball plastic FBGA 56-pin plastic TSOP(I) (BGA-69P-M02) (FPT-56P-M04) www.DataSheet4U.com www.DataSheet4U.com MB84VD2118XA-85/MB84VD2119XA-85 (Continued) 1. FLASH MEMORY Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to “PIN DESCRIPTION”) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program Minimum 100,000 write/erase cycles Sector erase architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. Boot Code Sector Architecture MB84VD2118XA : T...