MODULE. MC-45V16AD641 Datasheet

MC-45V16AD641 Datasheet PDF

Part MC-45V16AD641
Description 16M-WORD BY 64-BIT Virtual Channel SYNCHRONOUS DYNAMIC RAM MODULE
Feature MC-45V16AD641; DATA SHEET MOS INTEGRATED CIRCUIT MC-45V16AD641 VirtualChannel TM 16M-WORD BY 64-BIT SYNCHRONOUS .
Manufacture NEC
Datasheet
Download MC-45V16AD641 Datasheet




MC-45V16AD641
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45V16AD641
16M-WORD BY 64-BIT
VirtualChannelTM SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45V16AD641 is a 16,777,216 words by 64 bits VirtualChannel synchronous dynamic RAM module on
which 16 pieces of 64M VirtualChannel SDRAM : µPD4565821 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
16,777,216 words by 64 bits organization
Clock frequency and access time from CLK
Part number
Read Clock
Access
Maximum supply current mA
latency frequency time
Operating
Refresh
MC-45V16AD641KF-A75 2
MHz
(MAX.)
133
from CLK Prefetch Restore
Channel
ns (MAX.)
read / write (Burst)
5.4 880
720
Auto
1280
Self
16
MC-45V16AD641KF-A10
100 6
840
600 1120
MC-45V16AD641EF-A75
133 5.4
880
720 1280
MC-45V16AD641EF-A10
100 6
840
600 1120
Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Dual internal banks controlled by BA0 (Bank Select)
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and 16)
5 Read latency (2)
Prefetch Read latency (4)
Auto precharge and without auto precharge
Auto refresh and Self refresh
Single 3.3 V ± 0.3 V power supply
Interface: LVTTL
Refresh cycle: 4K cycles / 64 ms
168-pin dual in-line memory module (Pin pitch = 1.27 mm)
Unbuffered type
Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13823EJ6V0DS00 (6th edition)
Date Published June 2000 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1998



MC-45V16AD641
MC-45V16AD641
5 Ordering Information
Part number
Clock
frequency
MHz (MAX.)
MC-45V16AD641KF-A75
133
Read
latency
2
MC-45V16AD641KF-A10
100
MC-45V16AD641EF-A75
133
MC-45V16AD641EF-A10
100
Prefetch
read
latency
Package
Mounted devices
4 168-pin Dual In-line
16 pieces of µPD4565821G5
Memory Module (Socket Type) (10.16 mm (400) TSOP (II)) (Rev.K)
Edge connector : Gold plated 16 pieces of µPD4565821G5
34.93 mm height
(10.16 mm (400) TSOP (II)) (Rev.E)
2 Data Sheet M13823EJ6V0DS00



MC-45V16AD641
MC-45V16AD641
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85 VSS
86 DQ32
87 DQ33
88 DQ34
89 DQ35
90 Vcc
91 DQ36
92 DQ37
93 DQ38
94 DQ39
VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
95 DQ40
DQ8
11
96 VSS
VSS 12
97 DQ41
DQ9
13
98 DQ42 DQ10 14
99 DQ43 DQ11 15
100 DQ44 DQ12 16
101 DQ45 DQ13 17
102 Vcc
Vcc 18
103 DQ46
DQ14
19
104 DQ47
DQ15
20
105 NC
NC 21
106 NC
NC 22
107 VSS
VSS 23
108 NC
NC 24
109 NC
NC 25
110 Vcc
Vcc 26
111 /CAS
/WE 27
112
DQMB4
DQMB0
28
113
DQMB5
DQMB1
29
114 /CS1
/CS0
30
115 /RAS
NC 31
116 VSS
VSS 32
117 A1
A0 33
118 A3
A2 34
119 A5
A4 35
120 A7
A6 36
121 A9
A8 37
122
BA0 (A13)
A10
38
123 A11
A12 39
124 Vcc
Vcc 40
125 CLK1
Vcc 41
126 NC
CLK0
42
127 VSS
VSS 43
128 CKE0
NC 44
129 /CS3
/CS2
45
130
DQMB6
DQMB2
46
131
DQMB7
DQMB3
47
132 NC
NC 48
133 Vcc
Vcc 49
134 NC
NC 50
135 NC
NC 51
136 NC
NC 52
137 NC
NC 53
138 VSS
VSS 54
139 DQ48 DQ16 55
140 DQ49 DQ17 56
141 DQ50 DQ18 57
142 DQ51 DQ19 58
143 Vcc
Vcc 59
144 DQ52 DQ20 60
145 NC
NC 61
146 NC
NC 62
147 NC
CKE1
63
148 VSS
VSS 64
149 DQ53 DQ21 65
150 DQ54 DQ22 66
151 DQ55 DQ23 67
152 VSS
VSS 68
153 DQ56 DQ24 69
154 DQ57 DQ25 70
155 DQ58 DQ26 71
156 DQ59 DQ27 72
157 Vcc
Vcc 73
158 DQ60 DQ28 74
159 DQ61 DQ29 75
160 DQ62 DQ30 76
161 DQ63 DQ31 77
162 VSS
VSS 78
163 CLK3
CLK2
79
164 NC
NC 80
165 SA0
WP 81
166 SA1
SDA
82
167 SA2
SCL 83
168 Vcc
Vcc 84
/xxx indicates active low signal.
A0 - A12
: Address Inputs
[Row: A0 - A12, Column: A0 - A6]
BA0 (A13)
: VirtualChannel SDRAM
Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0, CKE1
: Clock Enable Input
/CS0 - /CS3
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE : Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL : Clock Input for PD
VCC : Power Supply
VSS : Ground
WP : Write Protect
NC : No Connection
Data Sheet M13823EJ6V0DS00
3







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