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MC54F148 Datasheet

Part Number MC54F148
Manufacturers Motorola
Logo Motorola
Description 8-LINE TO 3-LINE PRIORITY ENCODER
Datasheet MC54F148 DatasheetMC54F148 Datasheet (PDF)

8-LINE TO 3-LINE PRIORITY ENCODER The MC54/74F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits. • Encodes Eight Data Lines in Priority • Provides 3-Bit Binary Priority Code • Input Enable Capability • Signals When Data Present on Any Input • Cascadable for Priority Encoding of n .

  MC54F148   MC54F148






Part Number MC54F14
Manufacturers Motorola
Logo Motorola
Description SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS
Datasheet MC54F148 DatasheetMC54F14 Datasheet (PDF)

SCHMITT TRIGGERS DUAL 4-INPUT NAND/HEX INVERTERS The MC54/74F13 and MC54/74F14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole.

  MC54F148   MC54F148







8-LINE TO 3-LINE PRIORITY ENCODER

8-LINE TO 3-LINE PRIORITY ENCODER The MC54/74F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits. • Encodes Eight Data Lines in Priority • Provides 3-Bit Binary Priority Code • Input Enable Capability • Signals When Data Present on Any Input • Cascadable for Priority Encoding of n Bits CONNECTION DIAGRAM DIP (TOP VIEW) VCC EO GS I3 I2 I1 I0 A0 16 15 14 13 12 11 10 9 12 I4 I5 (10) I0 (11) I1 3456 I6 I7 E1 A2 LOGIC DIAGRAM 78 A1 GND (15) EO (14) GS (12) I2 (13) I3 (9) A0 (1) I4 (2) I5 (7) A1 (3) I6 (4) I7 (6) A2 (5) E1 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-59 MC54/74F148 8-LINE TO 3-LINE PRIORITY ENCODER FAST™ SHOTTKY TTL 16 1 J .


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