MC68HC68R2

® MOTOROLA Advance Information 8-BIT SERIAL STATIC RAMs The MC68HC68Rl and MC68HC68R2 are serially organized 128-word (MC68HC68Rl) or 256-word (MC68HC68R2) by 8-bit static random access memories (RAMs). These RAMs are intended for use in systems where minimum package and interconnect size, low power, and simplicity of use are desirable; for example, in systems utilizing synchronous serial 3-wire (clock, data in, data out) interfaces. Interface can I be made with the MC68HC05D2 without additional components, provided the MC68HC05D2 SPI control register bits CPHA and CPOL are set. Fully Static Operation Operating Voltage Range: 3 V to 5.5 V Maximum Standby Current = 2 p,A Directly Compatible with SPI Interface Separate Data Input and Data Output Pins Input Data and Clock Buffers Gated Off with Chip Enable Protocol for Fast Sequential Multiple Byte Accesses Minimum Data Retention Voltage: 2 V Small 8-Lead Plastic Package MC68HC68Rl MC68HC68R2 HCMOS (HIGH-DENSITY CMOS SILICON-GATE) 8-BIT SERIAL STATIC RAMs P SUFFIX PLASTIC PACKAGE CASE 626 PIN ASSIGNMENT S C K D 8 VDD SS 2 7 SDI See Note 3 . VSS 4 .. 6 SDO .5 CE NOTE Pin 3= N/C for MC68HC68Rl Pin 3=A7 for MC68HC68R2 ThiS document contains InformAtion on ~ product under development Motorola reserves the right to change or discontinue thIS product without notice 3-624 MC68HC68R1·MC68HC68R2 SIGNAL DESCRIPTION CHIP ENABLE AND SLAVE SELECT (CE AND SS) A high level on the CE pin, coincident with a low level...