MC68HC705MC4

HC705MC4GRS/D REV 1.5 68HC705MC4 SPECIFICATION (General Release) © January 17, 1995 CSIC System Design Group Austin, Texas The MC68HC705MC4 is an MCU device in a 28-pin DIP or SOIC package with the HC05 CPU core, a 16-bit timer including an output compare and two input captures, an 8-bit A/D converter with a 6 channel input multiplexer, a dual channel pulse width modulator (PWM), an SCI and a COP watchdog timer. The 4 K byte memory map has 3584 bytes of user ROM/EPROM and 176 bytes of RAM. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or...