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MC74F379 Datasheet

Part Number MC74F379
Manufacturers Motorola
Logo Motorola
Description QUAD PARALLEL REGISTER WITH ENABLE
Datasheet MC74F379 DatasheetMC74F379 Datasheet (PDF)

MC54/74F379 QUAD PARALLEL REGISTER The MC54/74F379 is a 4-bit register with a buffered common enable. This device is similar to the F175 but features the common Enable rather than common Master Reset. The F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When E is HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the .

  MC74F379   MC74F379






Part Number MC74F378
Manufacturers Motorola
Logo Motorola
Description PARALLEL D REGISTER WITH ENABLE
Datasheet MC74F379 DatasheetMC74F378 Datasheet (PDF)

MC54/74F378 PARALLEL D REGISTER WITH ENABLE The MC54/74F378 is a 6-bit register with a buffered common enable. This device is similar to the F174 but with common Enable rather than common Master Reset. The F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When the E input is LOW, new data is entered into the register on the LOWto-HIGH transition of the CP input. When the E input is HIGH.

  MC74F379   MC74F379







Part Number MC74F377
Manufacturers Motorola
Logo Motorola
Description OCTAL D FLIP-FLOP WITH ENABLE
Datasheet MC74F379 DatasheetMC74F377 Datasheet (PDF)

MC74F377 OCTAL D FLIP-FLOP WITH ENABLE The MC74F377 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is LOW. This device is supplied in a 20-pin package. • High Impedance NPN Base Inputs for Reduced Loading (20 µA in • • • • • HIGH and LOW States) Ideal for Addressable Register Applications Enable for Address and Data Synchronizatio.

  MC74F379   MC74F379







Part Number MC74F374
Manufacturers Motorola
Logo Motorola
Description OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Datasheet MC74F379 DatasheetMC74F374 Datasheet (PDF)

MC54/74F374 OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS The MC54/74F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • • • • Edge-triggered D-Type Inputs Buffered Positive Edge-triggered Clock 3-State Outputs for Bus-Oriented Applications ESD > 4000 V.

  MC74F379   MC74F379







Part Number MC74F373
Manufacturers Motorola
Logo Motorola
Description OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS
Datasheet MC74F379 DatasheetMC74F373 Datasheet (PDF)

MC54/74F373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS The MC54/74F373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL • Eight La.

  MC74F379   MC74F379







QUAD PARALLEL REGISTER WITH ENABLE

MC54/74F379 QUAD PARALLEL REGISTER The MC54/74F379 is a 4-bit register with a buffered common enable. This device is similar to the F175 but features the common Enable rather than common Master Reset. The F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When E is HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed. This circuit is designed to prevent false clocking by transitions on the E input. QUAD PARALLEL REGISTER WITH ENABLE FAST™ SCHOTTKY TTL • • • • Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Buffered Common Enable Input True and Complement Outputs CONNECTION DIAGRAM (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 E 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE Inputs E H L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change ORDERING INFORMATION Outputs Dn X H L Qn NC H L Qn NC L H 13 12 5 4 1 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC CP LOGIC SYMBOL Q3 Q2 Q1 Q0 15 14 10 11 7 6 2 3 D3 D2 D1 D0 E 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-176 MC54/74F379 LOGIC DIAGRAM D0 CP CP E Q E Q0 Q0 Q1 Q1 Q2.


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