MC92501

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC92501/D MC92501 Advance Information ATM Cell Processor The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM) layer device composed of dedicated high-performance ingress and egress cell processors combined with UTOPIA Level 2-compliant physical (PHY) and switch interface ports (see Block Diagram). The MC92501 is a second generation ATM cell processor in MotorolaÕs 92500 series. This document provides information on the new features offered by the second generation ATM cell processor. This document, combined with MC92500/D, provides the complete speciÞcation for the ATM cell processor. New Features of the MC92501: ¥ Implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and Bellcore Recommendations ¥ Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0 ¥ Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections ¥ UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface ¥ Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD) ¥ Change ABR RM Cell Priority ¥ Support for CLP Transparency Existing MC92500 Features: ¥ Full-Duplex Operation at Data Rates up to 155 Mbit/sec ¥ Performs Internal VPI and VCI Address Compression for up to 64K VCs ¥ CLP-Aware Peak, Average, and Burst-Length Policing with Programmable Tag/Drop Action Per Policer ¥ Supports up to 16 Physical Links Using...