MCM6208C

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6208C/D 64K x 4 Fast Static RAM The MCM6208C is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual–in–line and plastic small–outline J–leaded packages. Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 12, 15, 20, 25, and 35 ns Equal Address and Chip Enable Access Times Low Power Operation: 135 –165 mA Maximum AC Fully TTL Compatible — Three–State Output MCM6208C P PACKAGE 300 MIL PLASTIC CASE 724A–01 J PACKAGE 300 MIL SOJ CASE 810A–02 BLOCK DIAGRAM A1 A2 A3 A4 A6 A12 A13 A14 ROW DECODER MEMORY ARRAY 256 ROWS x 64 x 4 COLUMNS VCC VSS PIN ASSIGNMENT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A15 A14 A13 A12 A11 A10 DQ0 DQ1 DQ2 DQ3 W DQ0 DQ1 DQ2 DQ3 A0 A5 A7 INPUT DATA CONTROL COLUMN I/O COLUMN DECODER E VSS PIN NAMES A8 A9 A10 A11 A15 A0 – A15 . . . . . . . . . . . . . Address Input DQ0 – DQ3 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . ...