MCM62110

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM62110/D 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker The MCM62110 is a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola’s high–performance silicon–gate CMOS technology. The device integrates a 32K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers, two sets of output latches, active high and active low chip enables, and a parity checker. The RAM checks odd parity during RAM read cycles. The data parity error (DPE) output is an open drain type output which indicates the result of this check. This device has increased output drive capability supported by multiple power pins. In addition, the output levels can be either 3.3 V or 5 V TTL compatible by choice of the appropriate output bus power supply. The device has both asynchronous and synchronous inputs. Asynchronous inputs include the processor output enable (POE), system output enable (SOE), and the clock (K). The address (A0 – A14) and chip enable (E1 and E2) inputs are synchronous and are registered on the falling edge of K. Write enable (W), processor input enable (PIE) and system input enable (SIE) are registered on the rising edge of K. Writes to the RAM are self–timed. All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP have input data registers triggered by the rising edg...